-- entité VHDL de l'exo 2
library IEEE;
use  IEEE.STD_LOGIC_1164.all;
--entité VGA globale exo2
ENTITY VGAtop IS
  PORT (clk_50 : in STD_LOGIC; -- horloge 50MHz
-- valeurs à afficher sur  deux digits
     DeuxDigits : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-- en sortie nos cinq signaux VGA
     hsynch,vsynch,red,green,blue : out STD_LOGIC);
END VGAtop;

---------------------------------------------------------------------

-- partie VHDL de l'exo4 : picoBlaze avec un port d'entrée
-- et un port de sortie
-- deuxième version de la correction de l'exo1 du TP10
library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;
entity tp10exo1 is
  port (
  clk,reset : in std_logic;
  entrees : in std_logic_vector(7 downto 0);
  sorties : out std_logic_vector(7 downto 0)
  );
end tp10exo1;

architecture atp10 of tp10exo1 is
component kcpsm3 
    Port (      address : out std_logic_vector(9 downto 0); 
            instruction : in std_logic_vector(17 downto 0); 
                port_id : out std_logic_vector(7 downto 0); 
           write_strobe : out std_logic; 
               out_port : out std_logic_vector(7 downto 0); 
            read_strobe : out std_logic; 
                in_port : in std_logic_vector(7 downto 0); 
              interrupt : in std_logic; 
          interrupt_ack : out std_logic; 
                  reset : in std_logic; 
                    clk : in std_logic); 
end component;
component mpu_rom 
    Port (      address : in std_logic_vector(9 downto 0); 
            instruction : out std_logic_vector(17 downto 0); 
                    clk : in std_logic); 
end component;

signal s_sorties, s_sorties2, s_entrees: std_logic_vector(7 downto 0);
signal s_write_strobe,s_read_strobe : std_logic;
signal s_address : std_logic_vector(9 downto 0);
signal s_instruction : std_logic_vector(17 downto 0);
begin
  i1:kcpsm3 port map(address => s_address,
         instruction => s_instruction,
		port_id => open,
		in_port => s_entrees,
		out_port => s_sorties,
		read_strobe => s_read_strobe,
		write_strobe => s_write_strobe,
		interrupt =>'0',
		interrupt_ack => open,
		reset => reset,
		clk => clk);
  i2: mpu_rom port map(address => s_address,
                       instruction => s_instruction, 
		       clk => clk);
-- mémorisation des entrées
process(clk) begin
  if rising_edge(clk) then
    if s_read_strobe = '1' then
       s_entrees <= entrees;	 
	 end if;
  end if;
end process;  
-- mémorisation sorties							  
process(clk) begin
  if rising_edge(clk) then
    if s_write_strobe = '1' then
       s_sorties2 <= s_sorties;	 
	 end if;
  end if;
end process;  
sorties <= s_sorties2;  
end atp10;

-----------------------------------------------------------------------------------------------
;;; ceci n'est plus du VHDL mais de l'assembleur picoBlaze

;;;;;;; programme picoblaze pour exo 4
;;; examen final 2011
constant MAX, A0
namereg s0,i 
NAMEREG s1, nb 
namereg s2,j 
namereg s3,k

init:
	LOAD nb,00
debut: 
;lecture de l'état RS232
	OUTPUT nb,0
	CALL wait
	ADD nb,01
	JUMP debut
;=== triple boucle d'attente=== 
wait: 
	LOAD i,MAX 
loop:	 
		LOAD j,MAX 
loop_1: 
			LOAD k,MAX 
loop_2: 
			SUB k,01 
			JUMP NZ, loop_2 
		SUB j,01 
		JUMP NZ, loop_1 

	SUB i,01 
	JUMP NZ,loop 
	RETURN